1. Field of the Invention
The present invention relates to a laminated structure with an adhesive guard ring, and an image display device.
2. Description of the Related Art
Conventionally, a photolithographic method is performed to form electric wiring in semiconductor devices and electric circuits. With the photolithographic method, fine electric wiring patterns can be formed. However, the photolithographic method involves expensive equipment and complex procedures, which leads to an increase in the manufacturing cost. In order to reduce the manufacturing cost, a technology for forming an electric wiring pattern by directly applying a fine metal particle-dispersed liquid including fine metal particles onto a substrate, is drawing attention in recent years, and various methods are being proposed.
For example, patent document 1 describes the following method. First, a metal paste is formed by uniformly dispersing ultra-fine metal particles referred to as nano-metal ink, each particle having a diameter of 0.001 μm through 0.1 μm, in an organic solvent. Then, the metal paste is applied onto the surface of a substrate, and the coated substrate is dried and baked, thereby forming a metal coating having a thickness of 0.01 μm through 1 μm.
Patent document 2 discloses a laminated structure having fine patterns that can be easily formed, with the use of a wettability variable material whose critical surface tension changes by applying energy. The conductive layer in this laminated structure is made of a fine metal particle-dispersed liquid, with which an electrode can be formed in a high surface energy part having low water repellency on a film made of a wettability variable material. Accordingly, there is no need for expensive equipment and complex manufacturing procedures.
Patent documents 3 and 4 disclose the following semiconductor device. That is, a semiconductor including silicon (Si) is provided with a guard ring made of metal such as copper (Cu), whereby the guard ring extends along the periphery of the chip. This guard ring is provided in case the edge part of the chip is chipped or a crack is formed in an inter-layer insulating film, so as to prevent such damage from extending into a circuit formation region where an electric circuit for a memory or logic is formed.
Patent document 5 discloses a semiconductor device including a guard ring for improving adhering properties of films, and an inter-wiring layer insulating film having low permittivity for providing high-speed performance. Such an inter-layer insulating film having low permittivity contracts significantly due to heat, which degrades adhering properties between the insulating film and a metal film. Furthermore, such an inter-layer insulating film has high moisture-absorption properties, which leads to metal corrosion or detachment of the film. The guard ring structure of the semiconductor device can prevent these disadvantages.
Patent Document 1: Japanese Laid-Open Patent Application No. H03-281783
Patent Document 2: Japanese Laid-Open Patent Application No. 2005-310962
Patent Document 3: Japanese Laid-Open Patent Application No. H09-45766
Patent Document 4: Japanese Laid-Open Patent Application No. 2004-304124
Patent Document 5: Japanese Laid-Open Patent Application No. 2006-303545
However, the method described in patent document 1 has a problem in that the metal wiring, which is formed with a fine metal particle-dispersed liquid in which fine metal particles referred to as nano-metal ink are dispersed in water or an organic solvent, has a lower adhering property with respect to the substrate acting as a base, than that of metal wiring formed by a conventional vacuum deposition method or a sputtering method.
The method described in patent document 2 is advantageous in that a low surface energy part on a wettability variable material has high water repellency and thus has low moisture-absorption properties. However, due to this high water repellency, a film formed on the wettability variable material may have low adhering properties, which causes the film to be detached. Furthermore, moisture may enter through edge faces into the interface of the wettability variable material and the film formed on the wettability variable material, thereby degrading the reliability of the semiconductor device formed inside.
The methods described in patent documents 3, 4, and 5 are for forming a guard ring structure having a via that electrically connects the top and bottom wiring layers. In this structure, the via is embedded in the interlayer insulating film, and walls are formed by the wiring layers, which is a complex structure. In order to form such a guard ring with a semiconductor material including silicon, a photolithographic method needs to be performed, which requires expensive equipment and complex procedures, which leads to an increase in the manufacturing cost for the semiconductor device. Furthermore, the guard ring described in these documents does not prevent moisture from entering through edge faces, and thus cannot prevent the semiconductor device from degrading due to moisture.